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iming, timing, timing! That is the main concern of a digital designer charged with designing a semiconductor chip. What is it, how is it T described, and how does one verify it? The design team of a large digital design may spend months architecting and iterating the design to achieve the required timing target. Besides functional verification, the t- ing closure is the major milestone which dictates when a chip can be - leased to the semiconductor foundry for fabrication. This book addresses the timing verification using static timing analysis for nanometer designs. The book has originated from many years of our working in the area of timing verification for complex nanometer designs. We have come across many design engineers trying to learn the background and various aspects of static timing analysis. Unfortunately, there is no book currently ava- able that can be used by a working engineer to get acquainted with the - tails of static timing analysis. The chip designers lack a central reference for information on timing, that covers the basics to the advanced timing veri- cation procedures and techniques.
- Sales Rank: #1230344 in Books
- Published on: 2009-04-17
- Original language: English
- Number of items: 1
- Dimensions: 9.21" h x 1.31" w x 6.14" l, 2.15 pounds
- Binding: Hardcover
- 572 pages
From the Back Cover
Static Timing Analysis for Nanometer Designs: A Practical Approach is a reference for both beginners as well as professionals working in the area of static timing analysis for semiconductors. This book provides a blend of underlying theoretical background and in-depth coverage of timing verification using static timing analysis. The relevant topics such as cell and interconnect modeling, timing calculation, and crosstalk, which can impact the timing of a nanometer design are covered in detail. Timing checks at various process, environment, and interconnect corners, including on-chip variations, are explained in detail. Verification of hierarchal building blocks, full chip, including timing verification of special IO interfaces are covered in detail. Appendices provide complete coverage of SDC, SDF, and SPEF formats.
This book is written for professionals working in the area of chip design, timing verification of ASICs and also for graduate students specializing in logic and chip design. Professionals who are beginning to use static timing analysis or are already well-versed in static timing analysis will find this book useful.
Static Timing Analysis for Nanometer Designs serves as a reference for a graduate course in chip design and as a text for a course in timing verification for working engineers.
Most helpful customer reviews
11 of 11 people found the following review helpful.
good view from the outside; little insight on the insides
By EE Codewright
I'm disappointed with "Static Timing Analysis for Nanometer Designs"
by Bhasker and Chadha, a very expensive book that explains the basics
about static timing analysis, illustrated using a specific tool,
PrimeTime from Synopsys, Inc.
There's little to nothing about how timing analysis itself is done;
for that, try "Timing", by Sachin Sapapnekar. The focus in Bhasker
and Chadha is on constraint modeling, illustrated with the modeling
language SDC, Synopsys Design Constraints.
The physical book is well made and with good quality paper and print.
It is easy on the eyes -- there's lots of white space and timing
diagrams and basic examples, and no obvious typos. And lots and lots
of timing output reports, so many than one's eyes tend to glaze over,
but good to have when you need them. But in too many cases, the
figures are on different pages from the prose describing them, leading
to a lot of page flipping, which impedes learning.
The book is expensive -- it lists for $209.00, and the best price I
found was Amazon's at $165.87. For that kind of money, I want more
insight, more detail, more value. Yet I often felt like I was reading
a user's manual for a tool.
There is a conflict in exposition between simplicity (explain the
basic idea) and complexity (deal with the general case). I'm not a
timing expert, but for a "book [that] can be used as a reference for a
graduate course in chip design" (p. xivv), the exposition stayed quite
rudimentary. Most explanations are predicated on a common clock, and
some issues with setup and hold on multi-cycle paths are not
mentioned; e.g., no mention of the need to check that a multi-cycle
path does not violate setup or hold due to an intermediate clock edge;
I guess it does not occur "in most common scenarios" (page 262).
If you wade and wait long enough though (well more than half way, deep
into chapter 8 "Timing Verification" and into chapter 9 "Interface
Analysis"), you'll be rewarded with descriptions of more complicated
clocking schemes, and an indication of how the setup and hold edges
are determined for non-common clocks.
I was also disappointed with the bibliography -- great books dealing
with circuits and analysis were not mentioned, including "CMOS Circuit
Design, Layout, and Simulation, Revised Second Edition" by R. Jacob
Baker, and "Electronic Circuit and System Simulation Methods" by
Pillage (Pileggi), Rohrer, and Visweswariah.
Is the book clear, does it explain the basics well -- yes. Does the
book address how to *do* static timing analysis, clearly describe the
detailed semantics, or deal with synchronizers and complicated clock
domain crossings -- no. Is it worth the time to read and the money to
acquire -- depends on your needs. I expect it will be helpful; but it
still seems over priced.
[]
2 of 2 people found the following review helpful.
Complete reference
By SmithaS
I like how the explanations are very simple and to the point. this is a very good guide for primetime. My only complaint is that the book could have more examples. The book is very good for people who have already used primetime and is not for beginners.
0 of 0 people found the following review helpful.
Fantastic intro into STA
By Narayan
J Bhasker generally writes easy to understand books. This is another fine example.
This book covers a broad range of topics and is very complete and self contained. This is an excellent refresher on STA and can be used alongside any industry standard tool training one might take. Highly recommended. The price of the book is on the expensive side though.
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